MOSFET (metal-oxide-semiconductor field effect transistor) devices have many industrial applications, such as power amplifiers, power switches and low noise amplifiers to name a few. For many such applications, the gate leakage current is one of the device performance parameters of key importance as it may impact the MOSFET drive capacity and its associated static power loss. An ideal zero gate leakage current is impossible to achieve in practice. To substantially reduce the gate leakage current by tuning an existing wafer processing parameter set is known to be difficult. Another conventional technology for reducing the gate leakage current is the reduction of threshold voltage by device design to reduce the static power loss. But reduction of threshold voltage has other system ramifications such as a correspondingly reduced device noise margin against a false turn-on. Hence there exists a continued need of consistently fabricating an MOSFET with lower gate leakage current. This becomes especially important for a trench MOSFET chip where the fabrication process to integrate additional function at the same chip can induce damage to the trench MOSFET—specifically, to the gate oxide—causing an excessive gate leakage current.